The invention relates to a pipelined digital signal processor which may be more particularly described as a processor using a common data and control bus.
Digital computers typically include a memory, input-output circuitry, a controller and an arithmetic section. The memory provides a source for a computer program to control the computer and for data to be operated on by the arithmetic section. The arithmetic section includes circuits which provide means for manipulating data in a predetermined manner. The controller provides control signals for regulating timing of operation and transfers of data to be operated upon. The input-output circuitry provides means for transferring information between the computer and external devices.
To increase computational speed, some digital computers are arranged for pipelined operation. In a pipelined operation the arithmetic section includes a collection of specialized circuits capable of working simultaneously but altogether forming a general purpose organization. These specialized circuits operate independently, each performing a specific task in a general purpose procedure. The pipelined operation divides a process into several subprocesses which are executed by the individual specialized circuits. Successive ones of the subprocesses are carried out in an overlapped mode analogous to an industrial assembly line. New operands are applied at the input to the arithmetic section during each cycle. Different subsections of the arithmetic section perform their tasks in sequential order during subsequent cycles. A resultant is produced each cycle. Each specialized circuit performs its own task at the cyclic rate.
Control of a pipelined processor presents particularly perplexing problems because data and instructions become stacked up in pipelines during steady-state operation.
Heretofore a pipelined digital processor has been designed to transfer data words and instructions from memory to an arithmetic section and into a control section in respective pipelined streams. Data words are transferred from memory by way of one bus to the arithmetic section. Instructions are transferred from memory to the control section by way of another bus. These two separate busses alleviate bus contention and enable the pipelined data stream and the pipelined instruction steam to be transferred from section to section very rapidly. As a consequence, the rate of computation is enhanced.
A problem arises, however, when a processor designer desires to use this pipelined architecture in a processor to be fabricated as a single integrated circuit chip. The logic circuitry and the bus structure requirements of the processor use so much space on the chip that the chip becomes too expensive.